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SDRAM MODULE
KMM378S3320T
Preliminary KMM378S3320T
32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks, 4K Ref. 3.3V Synch. DRAMs GENERAL DESCRIPTION
The Samsung KMM378S3320T is a 32M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM378S3320T consists of eighteen CMOS 32M x 4 bit Synchronous DRAMs in TSOP-II 400mil packages, two 20 bits Drive ICs for input control signal and one PLL in 24-pin TSOP package mounted on a 200-pin glass-epoxy substrate. Two 0.1uF decopling capacitors are mounted on the printed circuit board for each SDRAM. The KMM378S3320T is a Dual In-line Memory Module and is intended for mounting into 200-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. * * * * * * *
FEATURE
* Performance range Max Freq. (Speed) KMM378S3320T-G8 125MHz (8ns) KMM378S3320T-GH 100MHz (10ns) KMM378S3320T-GL 100MHz (10ns) KMM378S3320T-G0 100MHz (10ns) Burst Mode Operation Auto & Self Refresh Capability (4096 cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8) Data Scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock PCB : Height(1,250mil), double sided component
PIN CONFIGURATIONS (Front Side / Back Side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Front VDD NC NC *IN *OUT NC NC VSS DQ67 DQ66 VDDQ DQ65 DQ64 VSS DQ63 DQ62 NC DQ61 DQ60 VDDQ NC NC VSS NC NC Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Front VDDQ DQ51 DQ50 VSS DQ49 DQ48 VDDQ DQ43 DQ42 VSS DQ41 DQ40 VDDQ A4 A5 VSS A8 A9 VDD NC CKE0 VSS CAS NC VDD Pin Front Pin Front DQ16 VSS NC NC VDDQ DQ15 DQ14 VSS DQ13 DQ12 VDDQ DQ7 DQ6 VSS DQ5 DQ4 VDDQ NC NC NC NC NC SCL NC VSS Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Back NC NC VSS REGE RFU RFU NC DQ71 DQ70 VSS DQ69 DQ68 VDDQ NC VSS NC DQ59 DQ58 VSS DQ57 DQ56 VDDQ DQ55 DQ54 VSS Pin Back Pin Back Pin Back VDD(Q) NC VSS VSS NC NC VDDQ DQ11 DQ10 VSS DQ9 DQ8 VDDQ DQ3 DQ2 VSS DQ1 DQ0 SDA SA0 SA1 SA2 VDD NC NC 51 VSS 76 52 RAS 77 53 VSS 78 54 *A12/CS2 79 A11 55 80 VDD 56 81 A0 57 82 A1 58 83 VSS 59 84 DQ35 60 85 DQ34 61 86 VDDQ 62 87 63 DQ33 88 DQ32 64 89 VSS 65 90 66 DQ27 91 67 DQ26 92 VDDQ 68 93 DQ25 69 94 70 DQ24 95 71 VSS 96 DQ19 72 97 DQ18 73 98 74 VDDQ 99 75 DQ17 100 151 CLK0 176 126 DQ53 152 VDD 177 127 DQ52 153 NC 178 128 VDDQ 154 CS0 179 129 DQ47 VSS 155 180 130 DQ46 BA1 156 181 131 VSS 157 A10(AP) 182 132 DQ45 VDD 158 183 133 DQ44 A2 159 184 134 VDDQ A3 160 185 135 DQ39 VSS 161 186 136 DQ38 DQ31 162 187 137 VSS 163 DQ30 188 138 DQ37 VDDQ 164 189 139 DQ36 DQ29 165 190 140 VDD 166 DQ28 191 141 A6 167 VSS 192 142 A7 DQ23 168 193 143 VSS DQ22 194 144 BA0(A13) 169 170 VDDQ 195 145 NC 171 DQ21 196 146 VDD DQ20 172 197 147 DQM VSS 173 198 148 WE VSS 174 NC 199 149 NC 175 NC 200 150
Note :1. "*" ; These pins are not used in this synchronous DRAM module. Here these pins are equal to No Connection. 2. In LVTTL interface, VDDQ=VDD and VSSQ=VSS
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0 Mar. '98
SDRAM MODULE
PIN NAMES
Pin Name A0~A11 BA0, BA1 DQ0 ~ DQ71 CLK0 CKE0 CS0 RAS CAS WE DQM REGE *IN, *OUT **SA0 ~ SA2 **SDA **SCL VDD VDDQ Vss RFU NC Function Address Input (multiplexed) SDRAM Bank Select Data Inputs / Outputs Clock Input Clock Enable Input Chip Select Input Row Address Storbe Colume Address Strobe Write Enable DQ Mask Enable Buffer Enable Unbuffered Physical Detect Input/Output (separate) Address input for EEPROM Serial Data I/O for PD Clock Input for PD Power Supply Power supply for Data Input/Output Ground Reserved Future Use No Connection CLK CS Clock input
Preliminary KMM378S3320T
INPUT FUNCTION DESCRIPTION
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down standby.
CKE
Row & column address are multiplexed on the same Address pins. Row address:RA0~RA11 Column address:CA0~CA9,CA11 Selects bank to be activated during row address latch BA0,BA1 time and selects bank for read/wirte during column address latch time. RAS CAS WE DQM DQ Latches row address on the positive edge of the CLK with RAS low. Enables row access & precharge. Latches column address on the positive edge of the CLK with RAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS ,WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data intput when DQM active Data inputs/outputs are multiplexed on the same pins. The device operates in the transparent mode when REGE is high. The A data is latched if CLK is held at a high or low logic level. If REGE is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLK. REGE is tied to Vcc through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode.
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
REGE
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SDRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 BWE0, BCKE0, BRAS0, BCAS0 B0A0~B0A11,B0BA0,B0BA1 BDQM0 DQ64~67 10 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 10 PCLK1 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 10 PCLK2 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3
Preliminary KMM378S3320T
D0
DQ68~71 10
CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 10 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 10 CLK CS CTL Add DQM DQ0~3 10 CLK CS CTL Add DQM DQ0~3 10 CLK CS CTL Add DQM DQ0~3 10 VSS
D9
D1
10
D10
DQ60~63
DQ56~59
D2
D11
DQ48~51 10
DQ52~55
D3
10
D12
DQ40~43
DQ44~47
D4
10
D13
B1A0~B1A11,B1BA0,B1BA1 DQ32~35 10 BCS1 BWE1,BCKE1, BRAS1,BCAS1
DQ36~39
D5
D14
DQ24~27 10
DQ28~31
BDQM1 DQ16~19 10 PCKL3
CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3 CLK CS CTL Add DQM DQ0~3
D6
DQ20~23
D15
D7
DQ8~11
D16
DQ12~15
10
D8
DQ0~3
D17
DQ4~7 10
Vcc 2G AGND 1G AVCL IY0 IY1 IY2 CDC2509 IY3 IY4 CLK FBOUT FIBIN PCLK0 PCLK1 PCLK2 PCLK3 PCLK4
A0,A1,A4,A5,A8,A9,A11 RAS,CAS CKE0 REGE PCLK4 10k Vcc A2,A3,A6,A7,A10 CS0 WE,DQM BA0,BA1
SN74ALVCH162836
B0A0,B0A1,B0A4,B0A5,B0A8,B0A9,B0A11 B1A0,B1A1,B1A4,B1A5,B1A8,B1A9,B1A11 BRAS0,BCAS0 BRAS1,BCAS1 BCKE0 CLK0 BCKE1
10 10pF
LE OE
3.3pF 10pF
SN74ALVCH162836
LE
B0A2,B0A3,B0A6,B0A7,B0A10 B1A2,B1A3,B1A6,B1A7,B1A10 BCS0 BCS1 BWE0,BDQM0 BWE1,BDQM1 B0BA0,B1BA0 B0BA1,B1BA1
Serial PD SCL A0 A1 A2 SDA
SA0 SA1 SA2
OE
REV. 0 Mar. '98
SDRAM MODULE
Preliminary KMM378S3320T
STANDARD TIMING DIAGRAM WITH PLL & REGISTER(CL=2,BL=4)
*2 *1
Control Signal(RAS,CAS,WE) REG
*3 DOUT
8 9 10 11 12 13 14 15 16 17 18 19
*1. Register Input
0 CLK 1 2 3 4 5 6 7
RAS CAS WE
*2. Register Output
RAS
td tr td tr
CAS WE
*3. SDRAM
CAS latency(refer to *1) =2CLK+1CLK tSAC tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1 Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2) =2CLK
tRDL
Row Active
Read Command
Precharge Command
Row Active
Write Command
Precharge Command
td, tr = Delay of Register (SN74ALVCH162836 of TI)
Note : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal because of the buffering in register (SN74ALVCH162836). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Dont Care
REV. 0 Mar. '98
SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 18 50
Preliminary KMM378S3320T
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high votlage Input low voltage Output high voltage Output low voltage Input leakage current(Inputs) Input leakage current (I/O pins) Symbol VDD VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -18 -1.5 Typ 3.3 3.0 0 Max 3.6 VDDQ +0.3 0.8 0.4 18 1.5 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT Min Max 22 22 14 22 22 16.5 Unit pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A11, CS0) Input capacitance (RAS, CAS, WE, CKE0) Input capacitance (CLK0) Input capacitance (BA0, BA1) Input capacitance (DQM) Data input/output capacitance (DQ0 ~ DQ71)
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SDRAM MODULE
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst Length =1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page Burst tCCD = 2CLKs tRC tRC(min) CKE 0.2V 3 2 CAS Latency
Preliminary KMM378S3320T
Version -8 -H -L -10
Unit
Note
Operating Current (One Bank Active) Precharge Standby Current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
2,160 1,980 1,980 1,890 18 18 270
mA
1
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N
mA 126 90 90 540 mA
mA
Active Standby Current in non power-down mode (One Bank Active)
ICC3NS
360 2,520 2,070 2,070 2,070
mA
Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC4 ICC5 ICC6
mA 1,890 2,070 1,890 1,890 3,600 27 2,970 mA mA
1 2 3
Note : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 2 Drive ICs.
REV. 0 Mar. '98
SDRAM MODULE
AC OPERATING TEST CONDITIONS(VDD = 3.45V 0.15V, TA = 0 to 70C)
Parameter Input levels (Vih/Vil) Input timing measurement reference level Output timing measurement reference level Output load condition Value 2.4 / 0.4 1.4 1.4 See Fig. 2
Preliminary KMM378S3320T
Unit V V V
3.3V
Vtt=1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0=50
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -8 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) 68 8 70 10 1 1 1 2 1 16 20 20 48 -H 20 20 20 50 100 70 10 80 12 Version -L 20 20 20 50 -10 20 24 24 50 ns ns ns ns us ns ns CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note
CAS latency=3 CAS latency=2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 0 Mar. '98
SDRAM MODULE
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS Latency=3 CAS Latency=2 CLK to valid output delay Output data hold time CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC Symbol Min CLK cycle time tCC 8 12 6 6 3 3 3 3 2 1 1 6 6 -8 Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 -H Max 1000 Min 10 12 6 7 -L Max 1000
Preliminary KMM378S3320T
-10 Min 10 13 7 7 3 3 3.5 3.5 2.5 1.5 1 7 7 ns ns ns ns ns ns 3,4 3,4 3 3 2 ns 2 ns 1, 2 Max 1000 ns 1
Unit
Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency=3 CAS Latency=2
Note : 1. Parameters depend on programmed CAS latency which is based on Reg. DIMM. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. This parameter is measured on both Register and SDRAM.
REV. 0 Mar. '98
SDRAM MODULE
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KMM378S3320T-8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 2 tRC 68ns 9 7 6 6 5 tRAS 48ns 6 5 4 4 4 tRP 20ns 3 2 2 2 2 tRRD 16ns 2 2 2 2 2 tRCD 20ns 3 2 2 2 2
Preliminary KMM378S3320T
(Unit : number of clock) tCCD 8ns 1 1 1 1 1 tCDL 8ns 1 1 1 1 1 tRDL 8ns 1 1 1 1 1
KMM378S3320T-H
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 2 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KMM378S3320T-L
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KMM378S3320T-10
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 3 2 2 2 tRC 80ns 8 7 7 6 5 tRAS 50ns 5 5 4 4 3 tRP 24ns 3 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 24ns 3 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 12ns 2 1 1 1 1
REV. 0 Mar. '98
SDRAM MODULE
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM
Preliminary KMM378S3320T
A13 A10/AP A12 ~ A11, A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3
X X X V V
X Row Address L H
Column Address (A0~A9,A11) Column Address (A0~A9,A11)
3 3
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
L L
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : . OP Code : Operand Code 1 A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 0 Mar. '98
SDRAM MODULE
PACKAGE DIMENSIONS
Preliminary KMM378S3320T
Units : Inches (millimeters)
0.118Min (3.00Min)
6.050 (153.70) 5.764 (146.40) Drive R 0.079 (R 2.000) 0.158 0.004 (4.000 0.100) (10.00) SPD 0.394 C 0.250 (6.350) 0.750 (19.05) 3.050 (77.47) 5.350 (135.89) B 0.250 (6.350) 1.050 (26.67) Drive 0.100Min (2.540Min) 0.150Max (3.81Max) TSOP 0.039 .002 (1.000 .050) 0.157 Min (4.000 Min) 0.050 0.0039 (1.270 0.10) 0.010Max (0.250 Max) 0.050 (1.270)
1.250 (31.75)
0.118 (3.000)
PLL
.118DIA .004 (3.000DIA .100) 0.350 (8.890)
A
0.250 (6.350)
0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100)
Detail A & B
(2.540 Min)
0.100 Min
Detail C
Tolerances :.005(.13) unless otherwise specified The used device is 32Mx4 SDRAM, TSOPII (Forward) SDRAM Part No. : KM44S32030T PLL Part No. : TI CDC2509 Drive IC : TI SN74ALVCH162836
REV. 0 Mar. '98

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